ECE-GY 6443 VLSI System and Architecture Design

3 Credits

This course continues from ECE-GY 6473 and covers top-down VLSI design using VHDL including structural design, modeling, algorithmic and register level design, synthesis, prototyping and implementation using FPGAs and methods to design for test (DFT). This course provides a solid background and hands-on experiences with the CMOS VLSI design process in which custom design techniques (covered in ECE-GY 6473) are married with HDL synthesis to produce complex systems. Students complete a project covering design partitioning, placement and routing, automated synthesis and standard cell design and use. The course explores how these techniques are used in designing ASICs, System-on-Chips (SoC) and advanced microprocessors.

Prerequisite(s): ECE-GY 6473 .
Weekly Lecture Hours: 3 | Weekly Lab Hours: 0 | Weekly Recitation Hours: 0